The present invention relates to integrated circuit isolation technology.
In integrated circuit technology, it is always necessary to separate the active regions of active devices (the "moat regions") one from another. In LSI and VLSI integrated circuits using MOS technology, this is usually performed by LOCOS (an acronym for "local oxidation of silicon"). In LOCOS, a patterned nitride is used to cover the areas which will be the moat regions, and the field oxide is then grown, by exposure to a high-temperature oxidizing ambient, in the exposed regions. However, it has long been recognized as a problem with this technology that the field oxide will not only grow vertically in the exposed regions, but will also grow laterally underneath the edges of the nitride mask. The lateral oxide encroachment (known as "bird's-beak") under the nitride is about half the field-oxide thickness, and this means that substantial real estate is wasted in this isolation technology.
A newer isolation technology, which is generally known by the acronym SWAMI (Sidewall Masked Isolation) or MF.sup.3 R (Modified Fully Framed Fully Recessed), uses a silicon etch and sidewall nitride layer to suppress the lateral encroachment of the field oxide. That is, after the patterned first nitride layer defines the active device regions, a silicon etch is then performed where the field oxide regions will be, and a sidewall nitride is deposited (over a pad oxide) on the sidewalls of this etched recess, to avoid encroachment of the field oxide into the active device regions. This general approach has the advantage of being easily integrated in standard MOS process flows, requires no additional photomasking steps, and can reduce moat encroachment to nearly zero.
However, this process has not generally been adopted in production use, since it still has several major shortcomings.
A further problem with the prior art is stress induced defects generated near the sidewalls of the moat areas during the field oxidation step. These defects degrade electrical characteristics. A pad oxide is normally deposited underneath both the first and second nitrides to avoid excessive mechanical stress caused by the thermal mismatch between the nitride and the silicon, but this pad oxide cannot be made too thick, or the moat encroachment will be excessive. That is, if the etch depth were made as large as would be desirable for fully recessed isolation, the pad oxide thickness required to avoid defect generation would be so large that moat encroachment would again be a problem. Thus, stress induced defects at the moat sidewalls have been a major problem with the so-called SWAMI or MF.sup.3 R methods as heretofore known, and this has posed a major barrier to adoption of these methods in production.
Thus it is an object of the present invention to provide a high-yield isolation method which does not provide large moat encroachment.
It is a further object of the present invention to provide an isolation technology which does not generate substantial moat encroachment, and which does not degrade yield through risk of substantial bird's-beaking.
It is a further object of the present invention to provide an isolation technology which does not risk substantial moat encroachment, and which does not generate substantial numbers of stress induced defects in the silicon substrate close to active device regions.
It is a further object of the present invention to provide a sidewall-nitride silicon-oxidation isolation technology which does not generate substantial numbers of stress induced defects in the silicon substrate close to active device regions.
It is a further object of the present invention to provide a sidewall-nitride silicon-oxidation isolation technology which is highly reliable.
It is a further object of the present invention to provide a sidewall-nitride silicon-oxidation isolation technology which does not degrade yield through risk of localized bird's-beaking.
A teaching of the present invention is that, after the sidewall nitride has been deposited on the etched silicon regions which will provide the isolation region, and the nitride has been cleared off the bottom of the etched silicon region which will provide the isolation region, a further silicon etch is performed. Preferably a first channel stop implant is performed and at least partially driven in before this further silicon etch. After the further silicon etch, a very heavy second channel stop implant may be performed. Thus, the deep channel stop implant stops leakage current between active device areas, but does not risk any significant diffusion of the channel stop species into active device regions whatsoever. At the same time, the short sidewall nitride avoids significant lateral encroachment of field oxide into active device regions.
A further problem of prior art SWAMI or MF.sup.3 R processes has been the double VT effect. That is, the subthreshold characteristics of the active devices can be degraded by a field-enhanced partial turn on at the edge of the channel, i.e. where the gate level crosses at the corner of the crystalline silicon adjacent to the oxide isolation region. That is, according to conventional electrostatics, the electric field will be enhanced at the corner of a conductive region, and this electric field enhancement will locally lower the turn on voltage of a parasitic field effect transistor adjacent to the recess sidewall.
Thus it is an object of the present invention to provide an isolation technology wherein the double VT effect is avoided.
A further advantage of the SWAMI or MF.sup.3 R technologies over LOCOS is that they are approximately planar. That is, since the silicon which is oxidized to form the field oxide is in a recess, the oxidation time and silicon etch depth can be selected such that the field oxide will grow to be approximately even with the top of the moat region. While this cannot be controlled to provide perfect planarity, it does provide less total vertical topographic excursion than the LOCOS process does. This in turn means that patterning of the upper levels in an integrated circuit, such as second metal, is easier, since one element of the vertical excursion has been greatly reduced.
Thus it is an object of the present invention to provide a substantially planar isolation technology with high yield.
It is a further object of the present invention to provide a substantially planar isolation technology which is not subceptible to localized bird's-beaking.
It is a further object of the present invention to provide a substantially planar isolation technology wherein stress-induced defects are not generated.
Another aspect in which it would desirable to improve over prior art LOCOS and SWAMI isolation technologies is radiation hardness. That is, ionizing radiation can generate substantial number of carrier, pairs, and holes will diffuse to the Si-SiO.sub.2 interface and be trapped there. Thus, the channel stop dosage should be large enough to not only avoid turn-on by the normal operating voltages, but also avoid turn-on (i.e. inversion of the silicon surface below the oxide) when trapped holes further increase the field. However, it is also necessary that the channel stop implant not substantially encroach on the active device regions, and this limits the dose which can be used for the channel stop implant in normal LOCOS or SWAMI. Thus, conventional MOS devices are not as radiation hard as they could be if a higher channel stop implant dose could be used without degrading active device characteristics.
Thus it is an object of the present invention to provide an isolation technology wherein radiation hardness is improved.
It is a further object of the present invention to provide an isolation technology wherein a very heavy channel stop implant dose can be used.
It is a further object of the present invention to provide radiation hard MOS integrated circuits.
It is a further object of the present invention to provide bulk CMOS integrated circuits having improved radiation hardness.
In a further embodiment of the present invention, where a channel stop implant is performed after a second silicon etch, very large doses can be used for the channel stop implant, since the regions exposed to the channel stop implant are relatively remote from the active regions.
A further embodiment of the present invention performs the original moat patterning not on a nitride/oxide stack, as is conventional, but on oxide/nitride/oxide stack. Thus, when the second nitride is conformally deposited, the stack over the moat regions is an oxide/nitride/oxide/nitride stack. When the second nitride is removed, the full thickness of the first nitride remains in place over the moat regions. Preferably the second oxide is stripped before field oxidation, so that there is no uncertainty as to the actual remaining thickness of the hardmask over the moat layers at the time of the channel stop implant. A further advantage of this additional oxide layer is that a heavier does and energy can be used for the channel stop, without significant penetration through the hard mask.
To achieve these and other objects and advantages, the present invention provides:
A method for fabrication of integrated circuits, comprising the steps of:
providing a monocrystalline silicon substrate;
covering predetermined portions of said substrate with a first patterned silicon nitride layer;
anisotropically etching a recess in said substrate where not covered by said first silicon nitride layer;
depositing a sidewall masking layer to cover sidewalls of said recess;
anisotropically etching said sidewall masking layer to substantially clear the bottom of said recess;
etching said substrate again, to make said recess deeper;
oxidizing exposed portions of silicon to form isolation oxide in said recess;
removing said first silicon nitride layer; and
forming desired active devices in portions of said substrate formerly covered by said first silicon nitride layer.